View SA572DR2_1118185.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SA572 Programmable Analog Compandor
The SA572 is a dual-channel, high-performance gain control circuit in which either channel may be used for dynamic range compression or expansion. Each channel has a full-wave rectifier to detect the average value of input signal, a linearized, temperaturecompensated variable gain cell (DG) and a dynamic time constant buffer. The buffer permits independent control of dynamic attack and recovery time with minimum external components and improved low frequency gain control ripple distortion over previous compandors. The SA572 is intended for noise reduction in high-performance audio systems. It can also be used in a wide range of communication systems and video recording applications.
Features http://onsemi.com MARKING DIAGRAMS
16 16 1 SOIC-16 WB D SUFFIX CASE 751G SA572D AWLYYWWG
* Independent Control of Attack and Recovery Time * Improved Low Frequency Gain Control Ripple * Complementary Gain Compression and Expansion with * * * * * * * * * * * * * *
External Op Amp Wide Dynamic Range - Greater than 110 dB Temperature-Compensated Gain Control Low Distortion Gain Cell Low Noise - 6.0 mV Typical Wide Supply Voltage Range - 6.0 V-22 V System Level Adjustable with External Components Pb-Free Packages are Available*
16
1
16 SA572N AWLYYWWG 1 16 SA 572 ALYW G G 1
1 PDIP-16 N SUFFIX CASE 648
16 1 TSSOP-16 DTB SUFFIX CASE 948F
Applications
Dynamic Noise Reduction System Voltage Control Amplifier Stereo Expandor Automatic Level Control High-Level Limiter Low-Level Noise Gate State Variable Filter
A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
PIN CONNECTIONS
D, N, DTB Packages*
TRACK TRIM A 1 RECOV. CAP A 2 RECT. IN A 3 ATTACK CAP A 4 DG OUT A 5 THD TRIM A 6 DG IN A 7 GND 8 16 VCC
15 TRACK TRIM B 14 RECOV. CAP B 13 RECT. IN B 12 ATTACK CAP B 11 DG OUT B 10 THD TRIM B 9 DG IN B
*D package released in large SO (SOL) package only. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
March, 2006 - Rev. 2
1
Publication Order Number: SA572/D
SA572
R1 (7,9) (6,10) 500 GAIN CELL 6.8kW DG (5,11)
(1,15) (3,13) 270 - + RECTIFIER 10kW - + BUFFER 10kW
(16)
P.S.
(8)
(4,12)
(2,14)
Figure 1. Block Diagram
PIN FUNCTION DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol TRACK TRIM A RECOV. CAP A RECT. IN A ATTACK CAP A DG OUT A THD TRIM A DG IN A GND DG IN B THD TRIM B DG OUT B ATTACK CAP B RECT. IN B RECOV. CAP B TRACK TRIM B VCC Tracking Trim A Recovery Capacitor A Rectifier A Input Attack Capacitor A Variable Gain Cell A Output Total Harmonic Distortion Trim A Variable Gain Cell A Input Ground Variable Gain Cell B Input Total Harmonic Distortion Trim B Variable Gain Cell B Output Attack Capacitor B Rectifier B Input Recovery Capacitor B Tracking Trim B Positive Power Supply Description
http://onsemi.com
2
SA572
MAXIMUM RATINGS
Rating Supply Voltage Operating Temperature Range Operating Junction Temperature Power Dissipation Thermal Resistance, Junction-to-Ambient N Package D Package DTB Package Symbol VCC TA TJ PD RqJA Value 22 -40 to +85 150 500 75 105 133 Unit VDC C C mW C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS Standard test conditions, VCC = 15 V, TA = 25C; Expandor mode (see Test Circuit). Input signals at unity gain level (0 dB) = 100 mVRMS at 1.0 kHz; V1 = V2; R2 = 3.3 kW; R3 = 17.3 kW, unless otherwise noted.
Characteristic Supply Voltage Supply Current Internal Voltage Reference Total Harmonic Distortion (Untrimmed) Total Harmonic Distortion (Trimmed) Total Harmonic Distortion (Trimmed) No Signal Output Noise DC Level Shift (Untrimmed) Unity Gain Level Large-Signal Distortion Tracking Error (Measured relative to value at unity gain) = [VO-VO (unity gain)] dB-V2dB Channel Crosstalk Symbol VCC ICC VR THD THD THD Test Conditions - No Signal - 1.0 kHz, CA = 1.0 mF 1.0 kHz, CR = 10 mF 100 Hz Input to V1 and V2 grounded (20-20 kHz) Input change from no signal to 100 mVRMS - V1 = V2 = 400 mV Rectifier Input V2 = +6.0 dB, V1 = 0 dB V2 = -30 dB, V1 = 0 dB 200 mVRMS into channel A, measured output on channel B PSRR 120 Hz Min 6.0 - 2.3 - - - - - -1.5 - - - 60 Typ - - 2.5 0.2 0.05 0.25 6.0 "20 0 0.7 "0.2 "0.5 - Max 22 6.3 2.7 1.0 - - 25 "50 +1.5 3.0 Unit VDC mA VDC % % % mV mV dB % dB dB dB
-2.5, +1.6 -
Power Supply Rejection Ratio
-
1mF 1% R3
70
-
100W + 22mF
dB
-15V
2.2mF V1
(7,9)
6.8kW
DG
(5,11) 82kW
17.3kW
5W CR = 10mF
- (2,14) (6,10) BUFFER 1kW + 2.2k + 2.2mF 270pF NE5234 V0
(4,12) CA = 1mF
(8)
(1,15)
2.2mF V2
3.3kW (3,13) R2 1%
RECTIFIER
(16) 0.1mF
+15V + 22mF
Figure 2. Test Circuit http://onsemi.com
3
SA572
Audio Signal Processing IC Combines VCA and Fast Attack/Slow Recovery Level Sensor In high-performance audio gain control applications, it is desirable to independently control the attack and recovery time of the gain control signal. This is true, for example, in compandor applications for noise reduction. In high end systems the input signal is usually split into two or more frequency bands to optimize the dynamic behavior for each band. This reduces low frequency distortion due to control signal ripple, phase distortion, high frequency channel overload and noise modulation. Because of the expense in hardware, multiple band signal processing up to now was limited to professional audio applications. With the introduction of the SA572 this highperformance noise reduction concept becomes feasible for consumer hi fi applications. The SA572 is a dual channel gain control IC. Each channel has a linearized, temperature-compensated gain cell and an improved level sensor. In conjunction with an external low noise op amp for current-to-voltage conversion, the VCA features low distortion, low noise and wide dynamic range. The novel level sensor which provides gain control current for the VCA gives lower gain control ripple and independent control of fast attack, slow recovery dynamic response. An attack capacitor CA with an internal 10 kW resistor RA defines the attack time tA. The recovery time tR of a tone burst is defined by a recovery capacitor CR and an internal 10 kW resistor RR. Typical attack time of 4.0 ms for the high-frequency spectrum and 40 ms for the low frequency band can be obtained with 0.1 mF and 1.0 mF attack capacitors, respectively. Recovery time of 200 ms can be obtained with a 4.7 mF recovery capacitor for a 100 Hz signal, the third harmonic distortion is improved by more than 10 dB over the simple RC ripple filter with a single 1.0 mF attack and recovery capacitor, while the attack time remains the same. The SA572 is assembled in a standard 16-pin dual in-line plastic package and in oversized SOL package. It operates over a wide supply range from 6.0 V to 22 V. Supply current is less than 6.0 mA. The SA572 is designed for applications from -40C to +85C.
BASIC APPLICATIONS
Description
The SA572 consists of two linearized, temperaturecompensated gain cells (DG), each with a full-wave rectifier and a buffer amplifier as shown in the block diagram. The two channels share a 2.5 V common bias reference derived from the power supply but otherwise operate independently. Because of inherent low distortion, low noise and the capability to linearize large signals, a wide dynamic range can be obtained. The buffer amplifiers are provided to permit control of attack time and recovery time independent of each other. Partitioned as shown in the block diagram, the IC allows flexibility in the design of system levels that optimize DC shift, ripple distortion, tracking accuracy and noise floor for a wide range of application requirements.
Gain Cell
VTI n
1 I 2G
) 1 IO 2 * VTIn IS
1I *1I 2G 2O IS
(eq. 1)
+ V TIn
I2 * I1 * IIN I 1 ) I IN * V TIn IS IS
where IIN +
V IN R1 R1 = 6.8 kW I1 = 140 mA I2 = 280 mA
IO is the differential output current of the gain cell and IG is the gain control current of the gain cell. If all transistors Q1 through Q4 are of the same size, equation 1 can be simplified to:
IO + 2 @ I IN @ I G * 1 I 2 * 2I 1 @ I G I2 I2
(eq. 2)
Figure 3 shows the circuit configuration of the gain cell. Bases of the differential pairs Q1-Q2 and Q3-Q4 are both tied to the output and inputs of OPA A1. The negative feedback through Q1 holds the VBE of Q1-Q2 and the VBE of Q3-Q4 equal. The following relationship can be derived from the transistor model equation in the forward active region.
DVBE
Q3Q4
+ D BE
Q1Q2
(VBE = VT IIN IC/IS)
The first term of equation 2 shows the multiplier relationship of a linearized two quadrant transconductance amplifier. The second term is the gain control feedthrough due to the mismatch of devices. In the design, this has been minimized by large matched devices and careful layout. Offset voltage is caused by the device mismatch and it leads to even harmonic distortion. The offset voltage can be trimmed out by feeding a current source within "25 mA into the THD trim pin.
http://onsemi.com
4
SA572
The residual distortion is third harmonic distortion and is caused by gain control ripple. In a compandor system, available control of fast attack and slow recovery improve ripple distortion significantly. At the unity gain level of 100 mV, the gain cell gives THD (total harmonic distortion) of 0.17% typ. Output noise with no input signals is only 6.0 mV in the audio spectrum (10 Hz-20 kHz). The output current IO must feed the virtual ground input of an operational amplifier with a resistor from output to inverting input. The non-inverting input of the operational amplifier has to be biased at VREF if the output current IO is DC coupled.
V+
1 1 I)I 2G 2O
I1 140mA
IO
A1 + Q4 Q3 - Q1 Q2
R1 6.8kW IG THD TRIM VREF VIN I2 280mA
Figure 3. Basic Gain Cell Schematic Rectifier
V+ I + V IN * V REF R2
The rectifier is a full-wave design as shown in Figure 4. The input voltage is converted to current through the input resistor R2 and turns on either Q5 or Q6 depending on the signal polarity. Deadband of the voltage to current converter is reduced by the loop gain of the gain block A2. If AC coupling is used, the rectifier error comes only from input bias current of gain block A2. The input bias current is typically about 70 nA. Frequency response of the gain block A2 also causes second-order error at high frequency. The collector current of Q6 is mirrored and summed at the collector of Q5 to form the full wave rectified output current IR. The rectifier transfer function is:
IR + V IN * V REF R2
(eq. 3)
R
VREF
+ A2 - Q5
D7
Q6 R2 VIN
If VIN is AC-coupled, then the equation will be reduced to:
IRAC + V IN(AVG) R2
The internal bias scheme limits the maximum output current IR to be around 300 mA. Within a "1.0 dB error band the input range of the rectifier is about 52 dB.
Figure 4. Simplified Rectifier Schematic
http://onsemi.com
5
SA572
Buffer Amplifier
In audio systems, it is desirable to have fast attack time and slow recovery time for a tone burst input. The fast attack time reduces transient channel overload but also causes low-frequency ripple distortion. The low-frequency ripple distortion can be improved with the slow recovery time. If different attack times are implemented in corresponding frequency spectrums in a split band audio system, high quality performance can be achieved. The buffer amplifier is designed to make this feature available with minimum external components. Referring to Figure 5, the rectifier output current is mirrored into the input and output of the unipolar buffer amplifier A3 through Q8, Q9 and Q10. Diodes D11 and D12 improve tracking accuracy and provide common-mode bias for A3. For a positive-going input signal, the buffer amplifier acts like a voltage-follower. Therefore, the output impedance of A3 makes the contribution of capacitor CR to attack time insignificant. Neglecting diode impedance, the gain Ga(t) for DG can be expressed as follows:
Ga(t) + (Ga INT * Ga FNL) e t A ) Ga FNL GaINT = Initial Gain GaFNL = Final Gain tA = RA * CA = 10 kW * CA
*t
where tA is the attack time constant and RA is a 10 kW internal resistor. Diode D15 opens the feedback loop of A3 for a negative-going signal if the value of capacitor CR is larger than capacitor CA. The recovery time depends only on CR * RR. If the diode impedance is assumed negligible, the dynamic gain GR (t) for DG is expressed as follows:
GR(t) + (G RINT * G RFNL) e t R ) GRFNL GR(t) + (G RINT * G RFNL) e t R ) GRFNL
tR = RR * CR = 10 kW * CR
*t *t
where tR is the recovery time constant and RR is a 10 kW internal resistor. The gain control current is mirrored to the gain cell through Q14. The low level gain errors due to input bias current of A2 and A3 can be trimmed through the tracking trim pin into A3 with a current source of "3.0 mA.
V+ Q8 Q9 Q10
Q17
IQ = 2IR2
IR2 X2 Q16
I
R
+
V IN R
10kW
- A3 + 10kW IR1
D15 D13
Q14
X2 Q18
D11
D12
CA
TRACKING TRIM
CR
Figure 5. Buffer Amplifier Schematic
http://onsemi.com
6
SA572
Basic Expandor
Figure 6 shows an application of the circuit as a simple expandor. The gain expression of the system is given by:
VOUT + V IN 2 2 @ R 3 @ V IN(AVG) I1 R2 @ R1 (I1 = 140 mA)
(eq. 4)
Both the resistors R1 and R2 are tied to internal summing nodes. R1 is a 6.8 kW internal resistor. The maximum input current into the gain cell can be as large as 140 mA. This corresponds to a voltage level of 140 mA*6.8 kW = 952 mV peak. The input peak current into the rectifier is limited to 300 mA by the internal bias system. Note that the value of R1 can be increased to accommodate higher input level. R2 and R3 are external resistors. It is easy to adjust the ratio of R3/R2 for desirable system voltage and current levels. A small R2 results in higher gain control current and smaller static and dynamic tracking error. However, an impedance
buffer A1 may be necessary if the input is voltage driven with large source impedance. The gain cell output current feeds the summing node of the external OPA A2. R3 and A2 convert the gain cell output current to the output voltage. In high-performance applications, A2 has to be low-noise, high-speed and wide band so that the high-performance output of the gain cell will not be degraded. The non-inverting input of A2 can be biased at the low noise internal reference Pin 6 or 10. Resistor R4 is used to bias up the output DC level of A2 for maximum swing. The output DC level of A2 is given by:
VOUT DC + V REF 1 ) R3 R4 * VB R3 R4
(eq. 5)
VB can be tied to a regulated power supply for a dual supply system and be grounded for a single supply system. CA sets the attack time constant and CR sets the recovery time constant.
R4 +VB
R3 17.3kW
- CIN1 + 2.2mF R5 100kW A1
CIN2 (7,9) 2.2mF
R1 6.8kW
DG
VREF
(5,11) (6,10) R6 1kW (2,14) (4,12) C1 2.2mF A2 VOUT
VIN
CIN3 2.2mF R2 3.3kW (3,13)
BUFFER
CA CR 1mF 10mF
(8)
(16) +VCC
Figure 6. Basic Expandor Schematic
Basic Compressor
Figure 7 shows the hook-up of the circuit as a compressor. The IC is put in the feedback loop of the OPA A1. The system gain expression is as follows:
VOUT + V IN I1 R2 @ R1 @ 2 R 3 @ V IN(AVG) (I1 = 140 mA)
1 2
RDC1, RDC2, and CDC form a DC feedback for A1. The output DC level of A1 is given by:
VOUT DC + V REF 1 ) R DC1 ) R DC2 R4
(eq. 6)
R DC1 ) RDC2 * VB @ R4
(eq. 7)
The zener diodes D1 and D2 are used for channel overload protection.
http://onsemi.com
7
SA572
R4 RDC1 9.1kW CDC 10mF C2 CIN1 VIN 2.2mF - R3 17.3kW C1 1kW R5 (6,10) VREF R1 (7,9) CIN2 2.2mF A1 + .1mF RDC2 9.1kW
D1
D2 VOUT
DG
(5,11) (2,14) (4,12) CR 10mF CA 1mF BUFFER
6.8kW
CIN3 2.2mF 3.3kW R2 (3,13)
(8) VCC
(16)
Figure 7. Basic Compressor Schematic Basic Compandor System
The above basic compressor and expandor can be applied to systems such as tape/disc noise reduction, digital audio, bucket brigade delay lines. Additional system design techniques such as bandlimiting, band splitting,
1 2 VRMS COMPRESSION IN
pre-emphasis, de-emphasis and equalization are easy to incorporate. The IC is a versatile functional block to achieve a high performance audio system. Figure 8 shows the system level diagram for reference.
2 REL LEVEL EXPANDOR OUT +29.54 dB ABS LEVEL dBM
3.0 V
+11.76
547.6 mV 400 mV
+14.77 +12.0
-3.00 -5.78
100 mV
0.0
-17.78
10 mV
-20
-37.78
1 mV
-40
-57.78
100 mV
-60
-77.78
10 mV
Figure 8. SA572 System Level
-80
-97.78
http://onsemi.com
8
SA572
C1
+
R1 3.3k RX ATTACK CAP CA
+
3, 13
2.2 mF
4, 12 1 mF 5, 11
BUFFER
2, 14 CR
+
RECOVERY CAP 10 mF
D G
6.8k R2
7, 9
C2
+
2.2 mF RDC2
R4 100k
RDC1 9.1k
+
9.1k CDC 10 mF
C3 VIN
+
R3 17.3k R5 1k C5
+
V+ 2 3 22 mF
-
2.2 mF TO THD TRIM PIN OF 572 PINS 6, 10
5532
+
1 VOUT DC
+
2.2 mF V-
VOUT
Figure 9. Automatic Level Control Automatic Level Control (ALC)
In the ALC configuration, the variable gain cell is placed in the feedback loop of the operational amplifier and the rectifier is connected to the input. As the input amplitude increases above the crossover point, the overall system gain decreases proportionally, holding the output amplitude constant. As the input amplitude decreases below the crossover point, the overall system gain increases proportionally, holding the output amplitude at the same constant level.
Gain + R1 R2 I1 2 R3 VIN(avg)
The output level is calculated using the following equation:
VOUT_LEVEL + R1 R2 I1 2 R3 VIN VIN (avg)
where:
VIN + p + 1.11 (for sine waves) VIN (avg) 22
R1 = 6.8 kW (Internal) R2 = 3.3 kW R3 = 17.3 kW I1 = 140 mA
where:
R1 = 6.8 kW (Internal) R2 = 3.3 kW R3 = 17.3 kW I1 = 140 mA
Note that for very low input levels, ALC may not be desired and to limit the maximum gain, resistor RX has been added.
Gain max. +
R1)Rx VREF
* R2 * IB 26 kW) * 10 kW
2 R3
The output DC level can be set using the following equation:
VOUT DC + 1) RDC1 ) RDC2 V REF R4
Rx ^ ((desired max gain)
where:
R4 = 100 kW RDC1 = RDC2 = 9.1 kW VREF = 2.5 V
http://onsemi.com
9
SA572
ORDERING INFORMATION
Device SA572D SA572DG SA572DR2 SA572DR2G SA572DTB SA572DTBG SA572DTBR2 SA572DTBR2G SA572NG SA572NG Description 16-Pin Plastic Small Outline Package 16-Pin Plastic Small Outline Package (Pb-Free) 16-Pin Plastic Small Outline Package 16-Pin Plastic Small Outline Package (Pb-Free) 16-Pin Thin Shrink Small Outline Package 16-Pin Thin Shrink Small Outline Package 16-Pin Thin Shrink Small Outline Package 16-Pin Thin Shrink Small Outline Package 16-Pin Plastic Dual In-Line Package 16-Pin Plastic Dual In-Line Package (Pb-Free) Package SO-16 WB SO-16 WB SO-16 WB SO-16 WB TSSOP-16* TSSOP-16* TSSOP-16* TSSOP-16* PDIP-16 PDIP-16 Temperature Range -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C Shipping 47 Units / Rail 47 Units / Rail 1000 / Tape & Reel 1000 / Tape & Reel 96 Units / Rail 96 Units / Tube 2500 / Tape & Reel 2500 / Tape & Reel 25 Units / Rail 25 Units / Rail
For information on / Tape and reel specifications, including part orientation and / Tape sizes, please refer to our / Tape and Reel Packaging Specification Brochure, BRD8011/D. *This package is inherently Pb-Free.
http://onsemi.com
10
SA572
PACKAGE DIMENSIONS
SOIC-16 WB D SUFFIX CASE 751G-03 ISSUE C
D
16 M 9
A
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_
H
B
1 16X
8
B TA
S
B B
S
0.25
M
A
h X 45_
SEATING PLANE
M
8X
0.25
E
A1
14X
e
T
C
PDIP-16 CASE 648-08 ISSUE T
L
-A-
16 9
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
F S
C
L
-T- H K G D
16 PL
SEATING PLANE
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
http://onsemi.com
11
SA572
PACKAGE DIMENSIONS
TSSOP-16 CASE 948F-01 ISSUE A
16X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16 9
2X
L/2
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
http://onsemi.com
12
EC CE ECC CEC
SECTION N-N
-W-
SA572/D

▲Up To Search▲

Price & Availability of SA572DR2

	To Download SA572DR2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .